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| M66335FP Facsimile Image Data Processor REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Description The M66335 is a facsimile image processing controller to turn into binary signals analog signals which have been output through photo-electric conversion by the image sensor. The image processing functions includes peak value detection, uniformity correction, resolution change, MTF compensation, correction, detection of background/character levels, error diffusion, separation of image zones, and designation of regions. This controller contains not only the analog processing circuit, the A/D converter of a 7-bit flash type and image processing memory, but also the image sensor and the interface circuit to the CODEC (Coder and Decoder). Therefore, this LSI alone is capable of image processing. Features * High speed scan (Max 2 ms/line, Typ 5 ms/line) * Compatibility with up to the B4 (8 pixels/mm, 16 pixels/mm) image sensor * Generation of control signals for the image sensor (CCD, CIS) For CCD: SH, CK1, CK2, RS For the contact sensor (CIS): SH, CK1, CK2 * Built-in analog processing circuit (equivalent to the M64291) Sample and hold circuit Gain control circuit Black level clamping circuit Reference internal power supply for the A/D converter * Built-in A/D converter of a 7-bit flash type * Built-in image processing memories Uniformity correction memory, Line memory, Error memory, correction memory * External output interface for converted binary data Serial output ( M66330) DMA output * External output interface for multivalued data DMA transfer of data compensated for uniformity * Various image processing functions Uniformity correction Resolution change from 50% to 200% (by the 1% step) MTF compensation (2-dimensional processing, capable of correction for each character/photo) correction (capable of correction for each character/photo) Detection of background/character levels Change to pseudo-halftone Error diffusion (64 tone steps through 6-bit processing) Organized dither (64 tone steps through the 8 x 8 matrix) Image zone separation (2-dimensional processing) * 5 V single power supply Application Facsimile, word processor and image scanner REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 1 of 58 M66335FP Block Diagram ADIN VWL VBL Vri+ Vri- 35 36 37 33 31 AVcc 18 34 DVcc 38 Vcc 3 11 17 42 52 62 Analog control 78 Image processing sequence control signal 4 SYSCK ACCK AIN LEVAJ C1 C2 BCMI BCMV GCAO BCMO PTIMB RS CK1 CK2 SH 19 20 26 27 28 29 22 30 7-bit A/D converter Analog signal processing circuit Image zone separation Detection of background/ character levels Resolution change MTF compensation Selection of conversion to binary processing 8 Image bus interface 5 6 7 Uniformity correction correction table SRDYB SVID SCLK STIMB DAKB DRQ INT RESETB WRB RDB CSB A0 to A4 D0 to D7 Error diffusion DMA control 75 76 77 9 12 13 14 15 Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix Organized dither 74 73 72 MPU bus interface 71 65 70 54 61 21 32 39 10 16 41 53 63 79 AGND DGND GND Pin Arrangement NC GND Vcc D7 D6 D5 MPU D4 interface D3 D2 D1 D0 GND VCC TEST6 TEST5 TEST4 TEST3 TEST2 Test pin TEST1 TEST0 TESTI TESTO VCC GND 64 63 62 61 59 58 57 56 54 53 52 51 50 49 48 47 46 45 43 42 41 60 55 44 MPU interface DMA interface System clock NC A0 A1 A2 A3 A4 CS RD WR RESET DAK DRQ INT SYSCK GND NC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 12 13 14 15 16 17 18 19 23 20 21 22 24 11 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 M66335FP 33 32 31 30 29 28 27 26 25 NC DGND DVCC VBL ADC black reference output VWL ADC white reference output ADIN ADC input AVCC Vri+ ADC white reference input AGND Vri- ADC black reference input BCMO BCMV Control signal for BCMI analog signal processing C2 C1 NC NC NC VCC Single-line ACCK cycle clock SVID CODEC SCLK interface STIM SRDY Sensor PTIM interface GND VCC RS Sensor CK1 interface CK2 SH GND VCC AVCC AIN Control LEVAJ signal for analog signal AGND processing GCAO NC NC NC: No Connection (Top view) Outline: PRQP0080GB-A (80P6N-A) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 2 of 58 M66335FP Table 1 Image Processing Functions Image Processing Functions Reading range Resolution Reading speed Uniformity correction correction Specifications Remarks * A4, B4 * 8 pixels/mm, 16 pixels/mm (for the horizontal scanning direction) * Typ: 5 ms/line; Max: 2 ms/line * White correction, black correction * Correction range: 50% * Logarithmic correction * Controlled through the system * * * correction memory is built-in * Capable of correction for each * * character/photo Correction memory is built-in Capable of correction for each character/photo clock Correction memory is built-in Readable from/writable in MPU MTF compensation * Laplacian filter circuit through 2dimensional processing Simple conversion to binary * Floating slice system through the detection circuit for background/character levels Pseudo-halftone * Error diffusion: 6-bit processing (for 64 * tone steps) Organized dither: 8 x 8 matrix (for 64 tone steps) luminance difference * Error buffer memory is built-in * 64 W x 6 bits dither memory is built-in Image zone separation Image reduction * 2-dimensional processing through * Range of the reduction rate: 50% to 100% (by the 1% step) * Capable of outputting the average line of a dropped line and the subsequent line instead of both lines Image enlargement * Range of the enlargement rate: 100% to 200% (by the 1% step) * Capable of outputting the average line of a repeated line and the subsequent line instead of the repeated line Image sensor control signal Analog processing * CIS image sensor (clock duty: 75%) * CCD image sensor * The sample/hold circuit, gain control amplifier, black level clamping circuit, and 7-bit A/D converter are built-in. REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 3 of 58 M66335FP Pin Description Item Sensor interface Pin Name SH Input/Output Output Function Outputs the shift pulse signal to transfer electric charges from the sensor's photoconductor component to its transferring component for CCD and the start signal to start the sensor reading circuit for CIS. Outputs the clock pulse signal to sequentially transfer out signaling electric charges from the sensor's transferring component for CCD and the clock pulse signal for the shift register of the sensor reading circuit for CIS. Reversed-phase pulses of CK1 Outputs the reset pulse to return the voltage at the floating capacitor of the CCD sensor to the initial one. Outputs the pulse motor control signal for the reading roller. Transfer start ready signal for data from CODEC Defines the data transfer section to CODEC Clock signal to transfer image data to CODEC Outputs image data in serial to CODEC DMA request signal to the external DMA controller to output in parallel image data through the MPU bus DMA acknowledge signal from the external DMA controller in response to the above DRQ signal Single-line termination interrupt System clock input pin Single-line cycle clock Input of the system reset. The cycle counter, register, F/F, and latch are reset. Chip select signal for MPU to access the M66335 Control signal for MPU to read data from the M66335 Control signal for MPU to write data to the M66335 Address signal to access various registers inside the M66335 8-bit two way buffer Positive power supply pin GND pin Test input pin. Hold this at "L". Test output pin. Set this open. Analog power supply pin (rated supply voltage: 5 V) Digital power supply pin (rated supply voltage: 5 V) Analog ground pin Digital ground pin Pin to input analog signals output from CCD or CIS (Signals from CCD are input through capacity coupling and those from CIS, with no clamping levels, are input directly.) Pin to control the frequency characteristic of the gain control circuit Pin to control the DC level of output signals of the gain control circuit. The output voltage, VGCAO, is obtained by the following equation: VGCAO = VLEVAJ + GV x VIN, where, VLEVAJ: voltage at LEVAJ VIN: input signal GV: gain of the gain control circuit VIN is the signal element corresponding to the signal level clamped through the input clamping circuit for CCD * CIS3 input or to the GND level for CIS1 * CIS2 input. Signal output pin of the gain control circuit CK1 Output CK2 RS PTIM SRDY STIM SCLK SVID DRQ DAK INT SYSCK ACCK RESET CS RD WR A0 to A4 Others D0 to D7 VCC GND TESTI, 0 to 6 TESTO AVCC DVCC AGND DGND AIN Output Output Output Input Output Output Output Output Input Output Input Output Input Input Input Input Input Input/Output -- -- Input Output -- -- -- -- Input CODEC interface DMA interface Clock MPU interface Power supply GND Sensor signal input part Gain control circuit C1, C2 LEVAJ Input Input GCAO Output REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 4 of 58 M66335FP Pin Description (cont.) Item Black level clamping circuit Pin Name BCMI BCMV BCMO Vri+ Input/Output Input Input Output Input Function Signal input pin to the black clamping circuit. Use this with capacity coupling with the GCAO pin. Pin to set the black level clamping voltage. Sets the black level of signals output from the BCMO pin for CCD signal processing. Signal output pin of the black level clamping circuit Output of the circuit to generate the A/D full-scale point reference voltage (3.8 V). Connected with VWL through the buffer inside the IC. To change the A/D reference voltage range, input a DC voltage from this pin. Output of the circuit to generate the A/D zero point reference voltage (1.8 V). Connected with VBL through the buffer inside the IC. To change the A/D reference voltage range, input a DC voltage from this pin. Signal input pin to the A/D converting circuit. Use this by connecting with the BCMO pin for CCD or with the GCAO pin for CIS. Input signals in the voltage range (1.8 V to 3.8 V) set through VWL and VBL. Output of the circuit generating the A/D full-scale reference voltage (3.8 V). Connected inside the IC with the A/D converter. Output of the circuit generating the A/D zero point reference voltage (1.8 V). Connected inside the IC with the A/D converter. A/D converter Vri- Input ADIN Input VWL VBL Output Output Absolute Maximum Ratings (Ta = -20 to +75C, unless otherwise noted) Item Supply voltage Input voltage Output voltage Analog supply voltage Supply voltage Reference voltage (white) Reference voltage (black) Analog input voltage Storage temperature Symbol VCC VI VO AVCC DVCC VWL VBL VAIN Tstg Ratings -0.3 to +6.5 -0.3 to VCC + 0.3 0 to VCC VCC - 0.3 to VCC + 0.3 VCC - 0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -55 to +150 Unit V V V V V V V V C Recommended Operational Conditions Item Supply voltage (for the digital system component) GND voltage Input voltage Analog supply voltage Analog GND voltage Supply voltage (for the digital system component) GND voltage Input range: VWL AVCC; VBL AGND Operating temperature Note: Symbol VCC GND VI AVCC AGND DVCC DGND VAIN Topr Min 4.75 -- 0 4.75 -- 4.75 -- 1.8 -20 Typ 5.0 0.0 -- 5.0 0.0 5.0 0.0 2.0 -- Max 5.25 -- VCC 5.25 -- 5.25 -- 2.2 +75 Unit V V V V V V V Vp-p C Connect the analog system component and the digital system component separately to power supply on the evaluation board for noise prevention. REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 5 of 58 M66335FP Electrical Characteristics (Ta = -20 to +75C, VCC = 5 V 5%, unless otherwise noted) Item "H" input voltage "L" input voltage Positive direction input threshold Negative direction input threshold Hysteresis value "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" input current "L" input current "H" input current in the off state "L" input current in the off state Analog input current Reference resistance Differential non-linear error Static current dissipation (during standby) Symbol VIH VIL VT+ VT- VH VOH VOL VOH VOL IIH IIL IOZH IOZL IAIN RL Ed ICCS Min 2.0 -- -- 0.6 -- VCC - 0.8 -- VCC - 0.8 -- -- -- -- -- -- -- -- -- Typ -- -- -- -- 0.2 -- -- -- -- -- -- -- -- -- 120 1.0 21 Max -- 0.8 2.4 -- -- -- 0.55 -- 0.55 1.0 -1.0 5.0 -5.0 1.0 -- -- 35 Unit V V V V V V V V V mA mA mA mA mA LSB mA VCC = 5.25 V VI = VCC, GND Test Conditions IOH = -12 mA IOL = 12 mA IOH = -4 mA IOL = 4 mA VCC = 5.25 V VI = 5.25 V VCC = 5.25 V VI = 0 V VCC = 5.25 V VO = 5.25 V VCC = 5.25 V VO = 0 V Timing Conditions (Ta = -20 to +75C, VCC = 5 V 5%, unless otherwise noted) Item System clock cycle System clock "H" pulse width System clock "L" pulse width System clock rise time System clock fall time Read pulse width Set-up time before read CS Set-up time before read A0 to A4 Set-up time before read DAK Hold time after read CS Hold time after read A0 to A4 Hold time after read DAK Write pulse width Set-up time before write CS Set-up time before write A0 to A4 Set-up time before write D0 to D7 Hold time after write CS Hold time after write A0 to A4 Hold time after write Hold time after STIM D0 to D7 SRDY Symbol tc (SYS) tw+ (SYS) tw- (SYS) tr (SYS) tf (SYS) tw (RD) tsu (CS-RD) tsu (A-RD) tsu (DAK-RD) th (RD-CS) th (RD-A) th (RD-DAK) tw (WR) tsu (CS-WR) tsu (A-WR) tsu (D-WR) th (WR-CS) th (WR-A) th (WR-D) th (STIM-SRDY) Min 50 25 25 -- -- 100 20 20 20 10 10 10 100 20 20 50 20 10 0 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 20 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 6 of 58 M66335FP Switching Characteristics (Ta = -20 to +75C, VCC = 5 V 5%, unless otherwise noted) Item Enable time for data output after read Disable time for data output after read Propagation time of DRO output after read Symbol tPZL (RD-D) tPZH (RD-D) tPLZ (RD-D) tPHZ (RD-D) tPHL (RD-DRO) Min -- 10 -- Typ -- -- -- Max 75 50 50 Unit ns ns ns ns ns Test Conditions CL = 150 pF CL = 50 pF Test Circuit Input Vcc Output Vcc RL = 1 k SW1 P.G Tested device SW2 50 CL GND RL = 1 k Item tPLH, tPHL tPLZ tPHZ tPZL tPZH SW1 Open Closed Closed Closed Open SW2 Open Open Closed Open Closed (1) Characteristics (10% to 90%) of the pulse generator (PG): tr = 3 ns; tf = 3 ns (2) Capacitance CL (= 150 pF) includes the stray capacitance of connections and input capacitance of the probe. System Clock tc (SYS) tf (SYS) tW+ (SYS) tW- (SYS) 3V 90% SYSCK 1.3 V 1.3 V 1.3 V 10% 10% 0V tr (SYS) 90% REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 7 of 58 M66335FP (1) Operation Mode The M66335 has three basic operations. * Peak value detection: Adjusting the peak value of analog signals output from the analog circuit to the white reference voltage (VWL) of the A/D converter built in the M66335. * Generation of data for uniformity correction: Generating data on a white reference original sheet for uniformity correction by the sensor unit and writing them to the memory for correction built-in the M66335. * Read: Reading original sheets, performing image processing of the read image data, and outputting in serial or parallel the indicated converted binary data. The M66335 is capable of performing the DMA transfer of multivalued data (6-bit data = D7 to D2, D1 = D0 = 0) after correction about uniformities. These three basic operations are performed in the following mode sequences for the CCD sensor and CIS sensor. The sensor is set through the register 00 (SENS). For the CCD Sensor AGC mode The peak value of the 16 line cycle is detected by setting the AGC command in the register 00 at "H". To escape this mode, set the AGC command at "L" after a 20 line cycle (or a cycle of 16 lines or more) passed since the start. This operation mode is started by setting the UNIF command in the register 00 at "H" after setting UMODE: "H" (white correction) in the register 00 and UNIFM: "L" (only white correction) in the register 01. Starting by the UNIF command also makes the system generate data for nonuniformity correction for white correction (for the 8 line cycle). To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. The read operation mode is started by setting the SCAN command in the register 00 at "H". To escape this mode, set the SCAN command at "L". UNIF mode (white) SCAN mode For the CIS Sensor AGC mode The peak value of the 16 line cycle is detected by setting the AGC command in the register 00 at "H". To escape this mode, set the AGC command at "L" after a 20 line cycle (or a cycle of 16 lines or more) passed since the start. When this operation mode is started by the UNIF command after setting UMODE: "L" (black correction) in the register 00 and UNIFM: "H" (black and white correction) in the register 01, the system also generates black data for nonuniformity correction for black correction (for the 8 line cycle). To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. In the case of only white correction, the setting is not necessary. Follow the instruction below. When this operation mode is started by the UNIF command in the register 00 after setting UMODE: "H" (white correction) in the register 00 and UNIFM: "L" (only white correction) in the register 01, the system also generates white data for non-uniformity correction for white correction (for the 8 line cycle). To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. The reading operation is started by setting the SCAN command in the register 00 at "H". To escape this mode, set the SCAN mode at "L". The signal operations and data flow in each basic operation are shown in the page 9 and 10, and the flowchart is in the page 26 and 27. UNIF mode (black) UNIF mode (white) SCAN mode REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 8 of 58 M66335FP Operations of Signals in the Peak Value Detection Operation BCAO GCAO VWL, VBL ADIN Vri+, Vri- Analog control Image processing sequence control signal Image zone separation ACCK SYSCK STIMB SCLK SVID C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit 7-bit A/D converter Detection of background/ character levels AIN Uniformity correction Resolution change MTF compensation correction table Error diffusion Selection of processing for conversion to binary Image bus interface DMA control Dither matrix Organized dither SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory MPU bus interface SRDYB INT DRQ DAKB RESETB CSB WRB RDB A0 to A4 D0 to D7 CODEC DMA MPU Flow of Data in the Creation of Data for Uniformity Correction BCAO GCAO VWL, VBL Vri+, Vri- ADIN Analog control Image processing sequence control signal Image zone separation Detection of background/ character levels ACCK SYSCK STIMB SCLK SVID C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit 7-bit A/D converter AIN Uniformity correction Resolution change MTF compensation correction table Error diffusion Selection of processing for conversion to binary Image bus interface DMA control Correction data memory Conversion table memory Line memory Error memory Dither matrix Organized dither SH CK1 CK2 RS PTIMB Sensor control MPU bus interface SRDYB INT DRQ DAKB RESETB CSB WRB RDB A0 to A4 D0 to D7 CODEC DMA MPU REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 9 of 58 M66335FP Flow of Data in the Reading Operation (for Output in Serial: Binary Data) BCAO GCAO VWL, VBL Vri+, Vri- ACCK SYSCK STIMB SCLK SVID Detection of background/ character levels ADIN Analog control Image processing sequence control signal Image zone separation Selection of processing for conversion to binary Image bus interface C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit 7-bit A/D converter AIN Uniformity correction Resolution change MTF compensation correction table Error diffusion DMA control Dither matrix Organized dither SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory MPU bus interface SRDYB INT DRQ DAKB RESETB CSB WRB RDB A0 to A4 D0 to D7 CODEC DMA MPU : image data : correction of compensation data Flow of Data in the Reading Operation (for Output in Parallel: Binary Data) BCAO GCAO VWL, VBL Vri+, Vri- ACCK SYSCK STIMB SCLK SVID Detection of background/ character levels Selection of processing for conversion to binary ADIN Analog control Image processing sequence control signal Image zone separation Image bus interface C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit 7-bit A/D converter AIN Uniformity correction Resolution change MTF compensation correction table Error diffusion DMA control Dither matrix Organized dither SH CK1 CK2 RS PTIMB Sensor control Correction data memory Conversion table memory Line memory Error memory MPU bus interface SRDYB INT DRQ DAKB RESETB CSB WRB RDB A0 to A4 D0 to D7 CODEC DMA MPU : image data : correction of compensation data Flow of Signals in the Reading Operation (for Multivated Data) BCAO GCAO ADIN VWL, VBL Vri+, Vri- ACCK SYSCK STIMB SCLK SVID Detection of background/ character levels Analog control Image processing sequence control signal Image zone separation Selection of processing for conversion to binary Image bus interface C1 C2 BCMV BCMI LEVAJ Image sensor Analog signal processing circuit 7-bit A/D converter AIN Uniformity correction Resolution change MTF compensation correction table Error diffusion DMA control Correction data memory Conversion table memory Line memory Error memory Dither matrix Organized dither SH CK1 CK2 RS PTIMB Sensor control MPU bus interface SRDYB INT DRQ DAKB RESETB CSB WRB RDB A0 to A4 D0 to D7 CODEC DMA MPU REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 10 of 58 M66335FP (2) Line Cycle and Reading Sequence The relationship between the line cycle and the reading sequence of the M66335 is shown in figure 1. The relationship between the CODEC interface operations and the reading sequence is shown in figure 2 and that between the DMA interface operations and the reading sequence is shown in figure 3. * Single-line cycle (1/ACCK) Defines the processing time per line of the M66335. The single-line cycle is decided by the line cycle counter value registers 03 and 04 (PRE_DATA), and the pixel transfer clock. The pixel transfer clock is 1/16 of SYSCK. 1 line cycle (1/ACCK) [NS] = line cycle counter value x pixel transfer clock cycle [NS] = (PRE_DATA + 1) x pixel transfer clock cycle [NS] = (PRE_DATA + 1) x 16/SYSCK [NS] After loading the PRE_DATA value, the line cycle counter generates the addresses of the following gate signals while counting down with the pixel transfer clock. * Sensor start pulse (SH) Image sensor start pulse. The point of the start pulse is decided by the uniformity correction range (UNIFG) and the value of the register 05. [ST_PL] The ST_PL value must be set according to the following formulas for each image sensor type. CCD: ST_PL = dummy pixels of the sensor + 2 CIS: ST_PL = 2 * Uniformity correction range (UNIFG) Defines the range where uniformity correction is performed. This range corresponds to the width of the sensor (B4 to A4). For the relationship between the sensor width and the uniformity correction range, see table 2. * AGC range (AGCG) Defines the range where peak value detection is performed. This range corresponds to the sensor width (B4 to A4). Auto gain control is performed for the whole width of the sensor (solid line) in the AGC mode and for the narrower width (dashed line) than the sensor width in the SCAN mode. For the relationship between the sensor width and the AGC range, see table 2. * Original sheet reading width Defines the reading width for original sheets. For original sheet widths narrower than the sensor width, the reading range (dashed line) is set, using the sensor center as the base center point. Therefore, the points for the original sheet should be based on the sensor center. For the relationship between the sensor width and the original sheet reading width, see table 3. * Pulse motor control signal (PTIM) Generates control signals for the pulse motor for the reading roller. REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 11 of 58 M66335FP PRE_DATA loading Countdown Line cycle (ACCK) Sensor start pulse (SH) ST_PL Uniformity correction range (UNIFG) AGC range (AGCG) Register 00 (SENS_W) Registers 03 and 04 (PRE_DATA) Register 00 (SENS_W) Register 05 (ST_PL) 0 Relationship with the registers Register 00 (SENS_W) Register 01 (SOURCE) Register 00 (SENS_W) Register 11, 12 (OFFSET) Original sheet reading range Pulse motor control (PTIM) 1 line cycle Figure 1 Line Cycle and the Reading Sequence ACCK SH SRDYB 1. 2. 3. 4. 5. SRDYB: L is taken in with a flow of SH, when scanning is started and PTIMB is output. (SSCAN: H) During the period that STIMB is L, converted binary data are output. SRDYB: H is taken in with a flow of ACCK, when the reading of one line ends. (SSCAN: L) INT is asserted with a flow of SSCAN. (INT: H) When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set L. Figure 2 CODEC Interface Operations and the Reading Sequence (Binary Data Output: Serial Output) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 12 of 58 M66335FP ACCK SH 4 1 2 DRQ DAKB RDB (Counter reset) (DMAFIN) : Output section 3 5 6 1. 2. 3. 4. SRDYB: L is taken in with a flow of SH, when scanning is started and PTIMB is output. (SSCAN: H) SRDYB: H is taken in with a flow of ACCK, when the reading of one line ends. (SSCAN: L) The internal counter reset signal is generated with a flow of SSCAN, and DRQ is asserted with a flow of SSCAN. After the internal counter is reset, DMA transfer is started. (The internal counter is counted up by one each time a pixel is transferred.) 5. When the value of the internal counter reaches the output pixel number, DMAFIN shifts to H, and DRQ is negated with a flow form DMAFIN and INT is asserted with a flow of DMAFIN. 6. When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set L. Figure 3 DMA Interface Operations and the Reading Sequence (Multivated Data Output) Table 2 Gate Signal Ranges for the Sensor Widths Sensor Width Gate Signal Uniformity correction range (UNIFG) AGC range (AGCG) AGC mode SCAN mode Resolution 200 dpi 400 dpi 200 dpi 400 dpi 200 dpi 400 dpi B4 2103/55 4207/111 2103/55 4207/111 2018/130 4037/261 A4 1943/215 3887/431 1943/215 3887/431 1584/564 3169/1129 Table 3 Original Sheet Reading Widths According to the Original Sheet Widths for the Sensor Widths Sensor Width Original Sheet Width B4 A4 Resolution 200 dpi 400 dpi 200 dpi 400 dpi B4 2102/54 4206/110 2102/54 4206/110 -- 1942/214 3886/430 A4 When original sheets narrower than the sensor width, cut out the original sheet width with the registers 11 to 14. (OFFSET, OUTLENGTH): (Region designation function) X Y X/Y X: Left end address Y: Right end address REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 13 of 58 M66335FP (3) Image Processing Function The M66335 converts image signals input from the image sensor into binary data. This includes the simple conversion of characters and the change of images with various densities into pseudo-half-tone. Before the conversion, distortions and characteristic degradations which signals from the image sensor almost always have must be corrected or compensated. Image zone separation must also be performed to realize optimal conversion-to-binary of the image for the possible shortest transmission time. Functions required for image processing are as follows. * * * * * * * Peak value detection Uniformity correction Resolution change (enlargement, reduction and averaging) MTF compensation correction Background/character level detection (simple conversion to binary) Change to pseudo-halftone Organized dither Error diffusion * Image zone separation * Designation of regions Peak Value Detection Because the A/D converter of the M66335 uses the input dynamic range at 2 Vp-p, the reference voltages (VWL, VBL) corresponding to the peak value are fixed. The peak value of analog signals output from the analog processing circuit must be detected before those signals are input to the A/D converter in order to adjust the analog signal peak value to the full-scale value of the converter. The peak value detection is performed by reading white data from the sensor in the AGC mode selected from its three modes (AGC, UNIF and SCAN) of the M66335. As shown in figure 4, preprocessing of peak value detection to increase the gain at the gain control is performed for a 8 line cycle and gain control processing to decrease the gain when the A/D converter over-flows is performed for another 8 line cycle after the start command (register 00: AGC) in the AGC mode. As a result, the gain changes as shown in figure 5. Peak value detection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Line cycle Preprocessing of peak value detection (increasing the gain) Gain control on the peak value (decreasing the gain) Figure 4 Peak Value Detection REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 14 of 58 M66335FP Preprocessing of peak value detection After the completion of preprocessing of peak value detection VWL White data The output level of the last pixel of the line is adjusted to VWL. VBL One line One line VWL The peak value of the sensor output in the line is adjusted to VWL. Gain control on the peak value After the completion of gain control on the peak value VBL Figure 5 Changes of the Gain in Peak Value Detection Uniformity Correction Uniformity correction is to correct shading distortion due to less light at each end of the light source and faded light around the lens, or high frequency distortion due to characteristic variations pixel by pixel in the image sensor. As shown in figure 7, the M66335 makes blocks each of two pixels, creates a set of uniformity correction data for each block, and write them to the built-in correction memory (SRAM: 1024 word x 6 bits) in the UNIF mode selected from its three modes (AGC, UNIF and SCAN). The correction data created each for two pixels are read from the built-in correction memory to correct the input image data consecutively in the SCAN mode. With the register 01 (UNIFS) set at "1", the uniformity is not implemented. With the register 02 (RES) set at "1", uniformity correction is performed on a block for 4 pixels. For uniformity correction, white correction or the combination of black correction and white correction can be selected according to the types of image sensors as shown in table 4. This is set in the register 00 (SENS, UMODE) and register 01 (UNIFM). To perform both black correction and white correction, the black correction must be done first. The M66335 implements the correction in the correction range of 50% as shown in figure 7. If a set of white correction data is beyond the correction range of 50%, the correction are not exactly performed as shown in figure 7. Therefore, ensure that input signals are within the range. Black level High frequency distortion Shading distortion White level 1 line Figure 6 Waveform of White Data Output from the Image Sensor REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 15 of 58 M66335FP Table 4 Uniformity Correction due to the Image Sensor Register Type of the Sensor Register 00 (SENS) 0 1 1 Creation of Uniformity Correction Data Register 00 (UMODE) 1 1 Period of black correction: 0 Period of white correction: 1 Selection of Correction Mode Register 01 (UNIFM) 0 0 1 Image Sensor CCD CIS Correction White correction White correction Black correction White correction VWL White correction + black correction Analog signal input White data 27 - 1 White correction Analog signal input VWL White data 27 - 1 50% 26 - 1 50% 26 - 1 VBL Black data 1 line 0 VBL 0 1 line Correction on over-range data (in white correction) VWL Analog signal input White data 27 - 1 50% 26 - 1 White data over the correction range VBL 0 Section over the correction range 1 line Figure 7 Uniformity Correction REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 16 of 58 M66335FP Resolution Change Resolution change is controlled through H/W in the horizontal scanning direction and through S/W in the vertical scanning direction. The sequence for resolution change is shown in figure 8. Horizontal Scanning Direction The scaling factor is written from the register 15 (CNV_D) to the built-in resolution change memory (100 W x 1 bit) bit by bit by 100 operations. MSSEL of the register 6 must be set at "0" (which specifies the horizontal scanning direction) before the scaling factor is written in the memory. The procedure to specify CNV_D is as follows. In the Case of Reduction Data written in the resolution change memory have the following meaning. "0": 1 pixel is output. "1": No pixel is output. (Example of reduction to 75%) 75 0's and 25 1's are written in the memory. The intervals of 1's should be as equal as possible to obtain the image with better quality. In the Case of Enlargement Data written in the resolution change memory have the following meaning. "0": 1 pixel is output. "1": 2 pixels are output. (Example of enlargement to 150%) 50 0's and 50 1's are written in the memory. The intervals of 1's should be as equal as possible to obtain the image with better quality as in the reduction. REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 17 of 58 M66335FP Vertical Scanning Direction Processing of lines to implement the scaling factor in the vertical scanning direction is decided for each line through the register. MSSEL of the register 6 must be set at "1" (which specifies the vertical scanning direction), and either "0" or "1" written in the register 15 (CNV_D) before the processing of each line. The timing for this setting is in the period between the first transition of the INT signal (synchronized with that of ACCK) and that of the SH signal (the start of taking the SRDY signal in). The procedure to specify CNV_D is as follows. In the Case of Reduction CNV_D indicates the current line read. "0": 1 line of data are output. "1": No line of data are output. In the Case of Enlargement CNV_D indicates the next line read. "0": 1 line of data are output with PTIM generated (paper driven). "1": 1 line of data are output with PTIM generated (paper not driven). (Paper not driven: the same line is read again.) Resolution change Enlargement/reduction is set in CONVX/CONVY. Specifying enlargement/reduction for horizontal/vertical scanning Specifying horizontal scanning Setting the scaling factor for resolution change in the horizontal scanning direction Specifying vertical scanning Setting the scaling factor for resolution change in the vertical scanning direction Start of reading a single line MSSEL is set at 0. Data setting in CNV_D (100 bits in quantity) MSSEL is set at 1. Data setting in CNV_D (1 bit in quantity) Setting of SRDY NO INT generated? YES End of reading a single line NO Page end? YES END Figure 8 Sequence of Resolution Change Setting Use the PTIMB signal as control signals for the pulse motor for the reading roller. The sequence for reduction is shown in figure 9 and that for enlargement in figure 10. REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 18 of 58 M66335FP ACCK SH : Output section 1 2 5 3 6 4 Reduced line Reduced line 1 0 1 0 1. At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting mode for enlargement/reduction in vertical scanning, the first line is set. 2. With a flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: H) 3. With a flow of SH, SRDYB: L is taken in, when scanning starts and PTIMB is output. (SSCAN: H) 4. During the period that STIMB is at L, converted binary data are output while the data for reduced lines are not output because STIMB for them are at H. 5. With a flow of ACCK, SRDYB: H is taken in, when the reading of the single line is completed. (SSCAN: L) 6. With a flow of SSCAN, INT is asserted. (INT: H) 7. With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is negated; and then SRDYB is set at L. Figure 9 Reduction Processing Sequence ACCK SH : Output section 1 2 5 3 6 4 Enlarged line Enlarged line 1 0 1 0 1. At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting mode for enlargement/reduction in vertical scanning, the first line is set. 2. With a flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: H) 3. With a flow of SH, SRDYB: L is taken in, when scanning starts and PTIMB is output while it is not output for enlarged lines. (SSCAN: H) 4. During the period that STIMB is at L, converted binary data are output. 5. With a flow of ACCK, SRDYB: H is taken in, when the reading of the single line is completed. (SSCAN: L) 6. With a flow of SSCAN, INT is asserted. (INT: H) 7. With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is negated; and then SRDYB is set at L. Figure 10 Enlargement Processing Sequence REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 19 of 58 M66335FP MTF Compensation As shown in figure 11, image data of characters or pictures photoelectrically converted by the sensor unit show degradation in resolution. MTF compensation function of the M66335 restores the resolution of those data and expands the apparent dynamic range by strengthening the high-pass frequency constituent with the Laplacian filter. Photoelectric conversion Photoelectric conversion Original (character) Image signal MTF compensation Data after compensation Photoelectric conversion Original (photo) Image signal MTF compensation Data after compensation Resolution compensation X' = X + ((X - A) + (X - B) + (X - C) + (X - D)) Where, : MTF compensation coefficient in the register 08 (MTF_C, MTF_I) In the above equation, is set according to the register 07: MODE (selection of conversion-into-binary mode) as follows: MODE: 00 (simple binary) = MTF_C MODE: 01 (organized dither) = MTF_I MODE: 10 (image zone separation) separation (character) = MTF_C for image zone separation (photo) = MTF_I for image zone MODE: 11 (error diffusion) = MTF_I Figure 11 MTF Compensation REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 20 of 58 M66335FP Correction correction according to the sensitivity characteristics (logarithmic characteristics) of human eyes is implemented to approximate the image data to natural images. To do this, the M66335 writes the correction table to the built-in SRAM and read the corrected values corresponding to read image data values from the SRAM. = 0.45 is considered to be the optimal for correction for thermal head printers. Figure 12 shows a characteristics example at = 0.45. correction processing is set through the register 06: GAMMA as follows. =1 = conversion table value = 1 for image zone separation (character) = conversion table value for image zone separation (photo) GAMMA: 11 = conversion table value for image zone separation (character) = 1 for image zone separation (photo) For the procedures of inputting/outputting of data, refer to the section on writing to/reading from the correction memory. GAMMA: 00 GAMMA: 01 GAMMA: 10 Image data 6 A <5, 0> DO <5, 0> 6 (Address) (Output) correction memory Data after correction 1.0 White 63 56 Image data after correction (memory output) DOUT 47 = 0.45 34 25 0 Dlow DIN Dup 1.0 =1 IF (DIN < Dlow) DOUT = 0 Black 0 Black: 0 8 16 32 Image data (address) 48 White: 63 Figure 12 Correction by Means of the Conversion Table IF (Dlow DIN < Dup) DOUT = DIN - Dlow Dup - Dlow IF (Dup DIN) DOUT = 1.0 ( ) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 21 of 58 M66335FP Background/Character Level Detection The M66335 uses not the fixed threshold system but the floating threshold system, where the optimal threshold for simple conversion-to-binary of objective pixels are continually generated by constantly detecting background/character levels. Accordingly, the threshold value proper for image data is generated without processing the data. The threshold value is used for the areas to be converted to binary when simple conversion-to-binary or image zone separation is selected as the mode of conversion to binary in reading data. : register 07 (MODE) * Background level counter When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to the data. When image data smaller (darker in light) than the current value are input, this counter counts down to approximate to the data. Setting of the rate of count-up/count-down following data input: register 0C (MAX_UP, MAX_DOWN) Setting of the lowest limit for background levels: register 0E (LL_MAX) * Character level counter When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to the data. When image data smaller (darker in light) than the current value are input, this counter counts down to approximate to the data. Setting of the rate of count-down following data input: register 0C (MIN_UP) Setting of the highest limit for character levels: register 0D (UL_MIN) Image data Background level detection counter Generation of the threshold value Character level detection counter Comparison Converted binary data This slope is decided through MAX_UP. This slope is decided through MAX_DOWN. Fixing of the background level White level Background level Lowest limit of the background level (LL_MAX) Input data Threshold level Character level Highest limit of the character level (UL_MIN) Black level This slope is decided through MIN_UP. Fixing of the character level Threshold level = (background level point - character level) x K + character level K = threshold factor for conversion to binary: register 07 (SLICE) Lowest limit of the background level (LL_MAX) > highest limit of the character level (UL_MIN) Figure 13 Background/Character Levels REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 22 of 58 M66335FP Error Diffusion The error diffusion, which is a conditional determination method, locally diffuses density errors between the original image and the result to obtain the best approximation. This generates images with good compatibility of gradation and resolution. This is operated by selecting the error diffusion in conversion-into-binary mode selection. : register 07 (MODE) In error diffusion, dithers as well as density errors are added to image data. The dithers are data as commonly used for the dither matrix. : register 08 (ERROR) correction must be performed in the error diffusion. * Organized dither The M66335 has built-in SRAM with a configuration of 64 words x 6 bits for organized dither memory. In the initial setting, write the threshold value proper for the preferred dither pattern to the dither memory after setting the dither matrix size. : register 07 (DITH) : register 10 (DITH_D) For the procedure of inputting/outputting data, refer to the section on writing to/reading from the dither memory. Dither matrix -32 m 17 10 2 9 11 5 12 8 20 15 25 19 Fmn K2 Fmn Gmn m * n * n Integrated error klEm - k, n - 1 (Note 2) K1 +- Fmn > 32 Gmn = 63 (white) Fmn < 32 Gmn = 0 (black) Weighting of the 1 error filter kl 2 2 4 4 2 1 Error Emn = Fmn - Gmn (Note 1) * Notes 1: Characterized by using the difference from the corrected value Fmn rather than that from the original pixel Fmn. 2: Errors before the point of remark are integrated. Error buffer memory Preceding line Current line * Fmn = Fmn + K1 (1 / kl) klEm - k, n - 1 + K2 (dither - 32) k, 1 k, 1 K1 = register 08 (error) K2 = register 08 (dither addition factor) Figure 14 Error Diffusion Method REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 23 of 58 M66335FP Image Zone Separation To make data conversion fit for each image zone, a black and white image is separated into the zones to be converted to binary and the gradation zones. The binary zone is processed through simple conversion to binary and the gradation zone through the error diffusion. : register 08 to 0E In the black and white image, each window of the gradation zone (photo) does not have a large difference of luminance in it. With this characteristic of the gradation zone, it is distinguished from the conversion-into-binary zone through the following method. Lmax: maximum illumination in window Lmin: minimum illumination in window Determining inequality 1: Lmax - Lmin > A (because the zone to be converted to binary has a large difference in luminance in it.): register 09 Difference (SEPA_A) Determining inequality 2: Lmin > B (for the wholly white area): register 0A Minimum (SEPA_B) Determining inequality 3: Lmax < C (for the wholly black area): register 0B Maximum (SEPA_C) If the window satisfies determination inequalities 1, 2 or 3, simple conversion to binary is applied. If the window does not satisfy any of determination inequalities 1, 2 and 3, change to pseudo-halftone is applied. White level = 63 Difference Lmax Minimum Lmin Maximum A Input data Lmin B C Black level = 0 Lmax - Lmin Lmax Figure 15 Image Zone Separation Region Designation Function The sensor width is fixed for A4 and B4. The region designation function is to output only the data for a region defined and designated in terms of output data after resolution change (or after uniformity correction for multivalued data). Registers 11 to 14 (OFFSET, OUTLENGTH) Output width Designated region OFFSET OUTLENGTH Figure 16 Cut-out Function REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 24 of 58 M66335FP (4) CODEC Interface (Binary Data Output) Serial Output SRDYB SH A B STIMB 10 4 12 (Equal scale, reduced scale) SCLK SVID 4 2 10 2 4 4 4 2 (Enlarged scale) SCLK 2 2 SVID Unit: 1/SYSCK Note: A is decided through the registers 05 (ST_PL) 11 and 12 (OFFSET), and B through the registers 13 and 14 (OUTLENGTH). Parallel Output Pixel SCLK SVID DRQ DAK RD D0 D1 D2 D3 D4 D5 D6 D7 N-1 N-2 N-3 N-4 N-5 N-6 N-7 N-8 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 1 2 3 4 5 6 7 8 Note: The 3-line handshake of SRDY, SH and STIM, which is the interface with CODEC, is the same as serial output. REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 25 of 58 M66335FP (5) DMA Interface (Multivalued Output) The DMA transfer of data after non-uniformity correction can be performed by setting P_O) of the register 01: at "1" (existence of DMA output) and M_B of that register at "1" (multivalue). With this setting, neither enlargement, nor reduction, nor 400 dpi of resolution can be set. SSCAN DRQ 2 (DMA counter reset signal) DAKB 1 4 RDB 3 (DMA counter signal) (DMAFIN) 5 INT D <7:2> 6 (XXXX): internal signal 1. On completion of reading one line, with a flow of SSCAN, the reset signal is entered in the DMA counter. 2. With a flow of the reset signal, DRQ shifts to "H", when the DMA transfer becomes ready. 3. With DAKB at "L" and a flow of RDB, DRQ shifts to "L", when multivalued data are output to D <7:2> during the period that RDB is at "L". 4. With a flow of DAKB, the DMA counter counts up and DRQ shifts to "H", when the DMA transfer becomes ready again. 5. The cycle of the above 3 and 4 is repeated until the DMA counter counts up to reach the number of output pixels set in the registers 13 and 14 OUTLENGTH subtracted by one. By that repetitive operation, DMAFIN shifts to "H" to terminate the DMA transfer when it reaches the set number. 6. With a flow of DMAFIN, INT shifts to "H", when CPU has an interrupt. 7. Reading is resumed from the next line by negating the INT signal through the register 17 (INTCLR). REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 26 of 58 M66335FP (6) Writing to/Reading from the Dither Memory, Correction Memory, Uniformity Correction Memory, and Resolution Change Memory The sequences of writing a dither pattern to and reading it from SRAM with a configuration of 64 words x 6 bits which is built in the M66335 for organized dither are shown below. Writing to the dither memory (MPU M66335) Initial setting (1) CSB A4 to A0 Initial setting (2) Memory address (0) Memory address (1) 07H 01H 10H 10H WRB D7 to D0 (Input) D6, D5 D0 = "1" DATA (0) DATA (1) 1 Reading from the dither memory (M66335 MPU) Initial setting (1) CSB A4 to A0 2 3 3 Initial setting (2) Memory address (0) Memory address (1) 07H 01H 10H 10H WRB D7 to D0 (Input) RDB D7 to D0 (Output) 1 2 D6, D5 D0 = "1" DATA (0) DATA (1) 4 4 1. D6 and D5 (DITH) of the register 07 are set to define the dither matrix size. 2. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the dither memory. 3. DITH_D is selected in the register 10, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the dither memory is incremented at the edge of the first transition of WR. (For writing) 4. DITH_D is selected in the register 10, and DATA (0) of the dither memory is read into the MPU bus (D5 to D0). The address counter of the dither memory is incremented at the edge of the first transition of RD. (For reading) A0 A4 A8 A12 A16 A20 A24 A28 A1 A5 A9 A13 A17 A21 A25 A29 A2 A6 A10 A14 A18 A22 A26 A30 A3 A7 A11 A15 A19 A23 A27 A31 A0 A8 A16 A24 A32 A40 A48 A56 A1 A9 A17 A25 A33 A41 A49 A57 A2 A10 A18 A26 A34 A42 A50 A58 A3 A11 A19 A27 A35 A43 A51 A59 A4 A12 A20 A28 A36 A44 A52 A60 A5 A13 A21 A29 A37 A45 A53 A61 A6 A14 A22 A30 A38 A46 A54 A62 A7 A15 A23 A31 A39 A47 A55 A63 Dither Matrix Addresses A0 A4 A8 A12 A1 A5 A9 A13 A2 A6 A10 A14 A3 A7 A11 A15 4 x 4 Matrix 4 x 8 Matrix 8 x 8 Matrix REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 27 of 58 M66335FP The sequences of writing correction table to and reading it from SRAM with a configuration of 64 words x 6 bits which is built in the M66335 for correction are shown below. Writing to the correction memory (MPU M66335) Initial setting (1) CSB A4 to A0 Memory address (0) Memory address (1) 01H 0FH 0FH WRB D7 to D0 (Input) D0 = "1" DATA (0) DATA (1) 1 Reading from the correction memory (M66335 MPU) 2 2 Initial setting (2) CSB A4 to A0 Memory address (0) Memory address (1) 01H 0FH 0FH WRB D7 to D0 (Input) RDB D7 to D0 (Output) 1 D0 = "1" DATA (0) DATA (1) 3 3 1. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the correction memory. 2. GAMMA_D is selected in the register 0F, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the correction memory is incremented at the edge of the first transition of WRB. (For writing) 3. GAMMA_D is selected in the register 0F, and DATA (0) of the correction memory is read into the MPU bus (D5 to D0). The address counter of the correction memory is incremented at the edge of the first transition of RDB. (For reading) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 28 of 58 M66335FP Uniformity correction data can be written to and read from SRAM for uniformity correction built in the M66335 through the MPU bus. With this operation, the uniformity data can be temporarily saved in the backup memory when the power is off. The sequences of writing and reading uniformity correction data are shown below. Writing to the uniformity correction memory (MPU M66335) Initial setting (1) CSB A4 to A0 Initial setting (2) Memory address (0) Memory address (1) 00H 01H 19H 19H WRB D7 to D0 (Input) D1 D0 = "1" DATA (0) DATA (1) 1 2 3 3 Reading from the uniformity correction memory (M66335 MPU) Initial setting (1) CSB A4 to A0 Initial setting (2) Memory address (0) Memory address (1) 00H 01H 19H 19H WRB D7 to D0 (Input) RDB D7 to D0 (Output) 1 2 D1 D0 = "1" DATA (0) DATA (1) 4 4 1. "0" (black correction) or "1" (white correction) is set in D1 (Umode) of the register 00. 2. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the uniformity correction memory. 3. UNIF_D is selected in the register 19, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the uniformity correction memory is incremented at the edge of the first transition of WRB. (For writing) 4. UNIF_D is selected in the register 19, and DATA (0) of the uniformity correction memory is read into the MPU bus (D5 to D0). The address counter of the uniformity correction memory is incremented at the edge of the first transition of RDB. (For reading) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 29 of 58 M66335FP The sequences of writing a resolution change table to and reading it from SRAM with a configuration of 100 words x 1 bit which is built in the M66335 for resolution change are shown below. Writing to the resolution change memory (MPU M66335) Initial setting (1) CSB Initial setting (2) Memory address (0) Memory address (1) A4 to A0 06H 01H 15H 15H WRB D7 to D0 (Input) D7 = "0" D0 = "1" DATA (0) DATA (1) 1 2 3 3 Reading from the resolution change memory (M66335 MPU) Initial setting (1) CSB A4 to A0 Initial setting (2) Memory address (0) Memory address (1) 06H 01H 15H 15H WRB D7 to D0 (Input) RDB D7 to D0 (Output) 1 2 D7 = "0" D0 = "1" DATA (0) DATA (1) 4 4 1. "0" (horizontal scan) is set in D7 (MSSEL) of the register 06. 2. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the resolution change memory. 3. CNV_D is selected in the register 15, and DATA (0) of the MPU bus (D0) is written in the memory. The address counter of the resolution change memory is incremented at the edge of the first transition of WRB. (For writing) 4. CNV_D is selected in the register 15, and DATA (0) of the resolution change memory is read into the MPU bus (D0). The address counter of the resolution change memory is incremented at the edge of the first transition of RDB. (For reading) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 30 of 58 M66335FP List of the M66335FP Registers R/W R/W R/W W W W W W W W W W W W W W R/W R/W W W W W W R/W W R/W R/W A4 to A0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H Default 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 1FH 20H -- -- 00H 00H 00H 00H -- 00H -- 00H 00H INTCLR GAIN <7:0> UNIF_D <5:0> AGCSTP SRDYS OUTLENGTH <7:0> OUTLENGTH <12:8> CNV_D SRDYB MAX_UP <1:0> MSSEL POL AVE DITH <1:0> CONVX <1:0> ERROR <1:0> D7 RESET SOURCE RES D6 SENS S/H_W LCMPS D5 SENS_W SH_W BLS D4 AGC UNIFS BLCMPS D3 UNIF P_O CCD D2 SCAN M_B CIS3 D1 UMODE UNIFM CIS2 D0 "L" CNTRST CIS1 PRE_DATA (7:0) PRE_DATA (13:8) ST_PL (7:0) CONVY <1:0> MTF_C <1:0> SEPA_A (5:0) SEPA_B (5:0) SEPA_C (5:0) MAX_DOWN <1:0> UL_MIN <5:0> LL_MAX <5:0> GAMMA_D (5:0) DITH_D (5:0) OFFSET <7:0> OFFSET <12:8> MIN_UP <1:0> GAMMA <1:0> SLICE <2:0> MTF_I <1:0> MODE <1:0> REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 31 of 58 M66335FP Register Structure Address 00H R/W R/W Description D7 RESET D6 SENS D5 SENS_W D4 AGC D3 UNIF D2 SCAN D1 UMODE D0 "L" (Default value: 00H) D7 0 1 RESET: System Reset Normal mode Reset mode With D7 = 1, the system is reset during the period that the write pulse is "L". (*) Write only D6 0 1 SENS: Sensor Type CCD CIS: (75% of clock duty) D5 0 1 SENS_W: Reading Width of the Sensor A4 B4 Controls start/stop of the AGC mode. D4 0 1 AGC: AGC Mode Stop Start D3 0 1 UNIF: UNIF Mode Stop Start Controls start/stop of the UNIF mode. D2 0 1 SCAN: SCAN Mode Stop Start Controls start/stop of the SCAN mode. D1 0 1 01H R/W UMODE: Uniformity Correction in the UNIF Mode Black Correction + White Correction Only White Correction Black correction White correction -- White correction D7 SOURCE D6 S/H_W D5 S/H_W D4 UNIFS D3 P_O D2 M_B D1 UNIFM D0 CNTRST (Default value: 00H) D7 0 1 SOURCE: Reading Width of the Original A4 B4 D6 0 1 S/H_W: S/W Pulse Width Normal (quadruple the system clock cycle) Normal multiplied by 0.5 REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 32 of 58 M66335FP Address 01H R/W R/W Description D5 0 1 SH_W: SH Pulse Width Normal (16 times the system clock cycle) Reverse of normal multiplied by 2 D4 0 1 UNIFS: Uniformity Correction Valid Invalid D0 is output in the form of LSB and D7 in the form of MSB. D3 0 1 P_O: DMA Output Without DMA output With DMA output D2 0 1 M_B: Processing Mode Binary Multivalue With the multivalue selected, data (6-bit) after nonuniformity correction can be output through the DMA transfer. D1 0 1 UNIF: Uniformity Correction in SCAN White correction Black correction + white correction With D0 = 1, the counter is reset during the period that the write pulse is "L". All the built-in RAM addresses are reset. (*) Write only D2 CIS3 D1 CIS2 D0 CIS1 (Default value: 00H) D0 0 1 02H W CNTRST: Address Counter Reset Normal mode Reset mode D7 RES D6 LCMPS D5 BLS D4 BLCMPS D3 CCD D7 0 1 RES: Resolution 200 dpi 400 dpi D6 0 1 Invalid Valid LCMPS: Line Clamping D5 0 1 BLS: Bit Clamping Invalid Valid D4 0 1 BLCMPS: Black Level Line Clamping Invalid Valid D3 0 0 0 1 D2 0 0 1 0 D1 0 1 0 0 D0 1 0 0 0 Sensors Compatible with Image Sensor Interfaces CIS1: sensors with the input level of 2 V or higher CIS2: sensors with the input level of under 2 V CIS3: sensors capable of line clamping CCD REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 33 of 58 M66335FP Address 03H R/W W Description D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) PRE_DATA <7:0> D7 to D0: PRE_DATA <7:0> the lowest order 8 bits of the single-line cycle counter value 04H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) PRE_DATA <13:8> D5 to D0: PRE_DATA <13:8> the highest order 6 bits of the single-line cycle counter value 05H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) ST_PL <7:0> D7 to D0: ST_PL <7:0> start pulse position to the sensor Set ST_PL = (dummy pixels of the sensor + 2). 06H W D7 MSSEL D6 AVE D5 CONVX D4 D3 CONVY D2 D1 D0 (Default value: 00H) GAMMA D7 0 1 MSSEL: Horizontal and Vertical Setting Horizontal Vertical When "with averaging" selected: For enlargement: inserted lines are the average of the preceding one and the current one. For reduction: the subsequent lines from removed lines are the average of the removed one and the current one. RES = 1 With the setting of 400 dpi, enlargement cannot be set. D6 0 1 AVE: Averaging Processing With averaging Without averaging D5 0 0 1 1 D4 0 1 0 1 CONVX: Enlargement/Reduction Mode in the Horizontal Scanning Direction Original scale Enlargement Reduction D3 0 0 1 1 D2 0 1 0 1 CONVY: Enlargement/Reduction Mode in the Horizontal Scanning Direction Original scale Enlargement Reduction REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 34 of 58 M66335FP Address 06H R/W W Description D1 0 0 1 1 D0 0 1 0 1 GAMMA: Correction Processing Character, photo: = 1 Character, photo: = download value Character: = 1; photo: = download value Character: = download value; photo: = 1 Note: Judgment between character and photo is based on the result of image zone separation. 07H W D7 POL D6 DITH D5 D4 MODE D3 D2 D1 SLICE D0 (Default value: 00H) D7 0 1 POL: Conversion-to-Binary Output Mode White: 1; black: 0 White: 0; black: 1 D6 0 0 1 1 D5 0 1 0 1 DITH: Dither Matrix Size 4x4 4x8 8x8 -- D4 0 0 1 1 D3 0 1 0 1 MODE: Selection of the Conversion-to-Binary Mode Simple binary Organized dither Image zone separation (simple binary + error diffusion) Error diffusion D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 SLICE: Threshold Factor for Conversion to Binary 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 35 of 58 M66335FP Address 08H R/W W Description D7 D6 D5 D4 ERROR D3 MTF_C D2 D1 MTF_I D0 (Default value: 00H) D5 0 0 1 1 D4 0 1 0 1 Error (Base) Strong (7/8) Strong (7/8) Weak (3/4) Weak (3/4) ERROR Rate of Dither Addition to Errors Weak (1/8) Strong (1/4) Weak (1/8) Strong (1/4) D3 0 0 1 1 D2 0 1 0 1 MTF_C: MTF Compensation Factor 1/4 1/2 1 0 Note: This is valid when MODE is simple binary or image zone separation (character). D1 0 0 1 1 D0 0 1 0 1 MTF_I: MTF Compensation Factor 1/4 1/2 1 0 Note: This is valid when MODE is organized dither, error diffusion or image zone separation (photo). 09H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) SEPA_A D5 to D0: SEPA_A Image zone separation parameter (differential) 0AH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) SEPA_B D5 to D0: SEPA_B Image zone separation parameter (minimum) 0BH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) SEPA_C D5 to D0: SEPA_C Image zone separation parameter (maximum) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 36 of 58 M66335FP Address 0CH R/W W Description D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) MAX_UP MAX_DOWN MIN_UP D5 0 0 1 1 D4 0 1 0 1 MAX_UP: Background Level Detection Clock for the Up Counter Ordinary (T = (single pixel cycle) x 32) Slow (T = (single pixel cycle) x 64) Fast (T = (single pixel cycle) x 16) Fastest (T = (single pixel cycle) x 8) D3 0 0 1 1 D2 0 1 0 1 MAX_DOWN: Background Level Detection Clock for the Down Counter Ordinary (T = (single pixel cycle) x 128) Slow (T = (single pixel cycle) x 256) Fast (T = (single pixel cycle) x 64) Fastest (T = (single pixel cycle) x 32) D1 0 0 1 1 0DH W D0 0 1 0 1 MIN_UP: Character Level Detection Clock for the Up Counter Ordinary (T = (single pixel cycle) x 128) Slow (T = (single pixel cycle) x 256) Fast (T = (single pixel cycle) x 64) Fastest (T = (single pixel cycle) x 32) D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 1FH) UL_MIN D5 to D0: UL_MIN Detection of background/character levels Highest limit of character levels 0EH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 20H) LL_MAX D5 to D0: LL_MAX Detection of background/character levels Lowest limit of background levels Lowest limit of background levels (LL_MAX) > highest limit of character levels (UL_MIN) 0FH R/W D7 D6 D5 D4 D3 D2 D1 D0 GAMMA_D <5:0> D5 to D0: GAMMA_D Built-in memory data 10H R/W D7 D6 D5 D4 D3 D2 D1 D0 DITH_D <5:0> D5 to D0: DITH_D Built-in dither memory data REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 37 of 58 M66335FP Address 11H R/W W Description D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) OFFSET <7:0> D7 to D0: OFFSET <7:0> Offset for cut-out Lowest order 8 bits 12H W D7 D6 D5 D4 D3 D2 OFFSET <12:8> D1 D0 (Default value: 00H) D3 to D0: OFFSET <12:8> Offset for cut-out Highest order 5 bits 13H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) OUTLENGTH <7:0> D7 to D0: OUTLENGTH <7:0> No. of output pixels Lowest order 8 bits 14H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value: 00H) OUTLENGTH <12:8> D3 to D0: OUTLENGTH <12:8> No. of output pixels Highest order 5 bits Note: OUTLENGTH <12:8> must be a multiple of 8. If a number of output pixels is not a multiple of 8, the remainder of the division must be omitted. 15H R/W D7 D6 D5 D4 D3 D2 D1 D0 CNV_D D0: CNV_D Indication of enlargement/reduction REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 38 of 58 M66335FP Address 16H R/W R/W Description D7 D6 D5 D4 D3 D2 AGCSTP D1 SRDYS D0 SRDYB (Default value: 00H) D2 0 1 AGCSTP: Gain Control Counter Gain control counter valid. Gain fixed. D1 0 1 SRDYS: SRDY Control SRDY control through the register SRDY control through the external pin In the case of data control through the register, the SDRYB input pin must be always set at "H". For the control through the register, the SRDY register must be controlled line by line. (*) Write only D2 D1 D0 D0 0 1 SRDYB: Data Transfer Start Ready Transfer allowed. Transfer not allowed. 17H W D7 D6 D5 D4 D3 INTCLR INT signals are negated by accessing to this address. 18H R/W D7 D6 D5 D4 D3 D2 D1 D0 GAIN <7:0> In reading: the current gain value of the gain control counter can be read. In writing: the gain value of the gain control counter can be set. However, this is valid only if AGCSTP = 1. 19H R/W D7 D6 D5 D4 D3 D2 D1 D0 With UMODE = 0, access to the uniformity correction memory for black correction is available. With UMODE = 1, access to the uniformity correction memory for white correction is available. UNIF <5:0> D5 to D0: UNIF_D Built- in uniformity correction memory data REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 39 of 58 M66335FP Description of the Operations of the Analog Circuits The configuration of the analog processing circuits is shown in figure 17. (1) Sensor Selection Circuit The four types of sensors in the table can be connected to the circuit. Register 02H CCD CIS1 CIS2 CIS3 Sensor Type CCD sensor CIS sensor which outputs light voltages (white voltage) of 3.5 V or lower CIS sensor which outputs light voltages (white voltage) of 2 V or lower CIS sensor which output shielding pixels for each line Black Max 500 mVp-p White Blanking element Signaling element The amplitudes of sensor signals are multiplied by -4 through the two operating amplifiers directly after the switch to select the CCD mode. (The waveforms of the signals are inverted at the same time.) As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2 V. Shielding pixel part Effective pixel part White Max 3.5 V Black 200 mV Signaling element The amplitude of signals input from the sensor are halved. Then, their reference potential is shifted up to 2.2 V. As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2 V. White Max 2 V Black 200 mV Signaling element The reference potential of signals input from the sensor is shifted up to 2.2 V. As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2 V. White 2 Vp-p Black Clamping level Shielding pixel part Signaling element Effective pixel part Sensor signals with a dark voltage of 2.2 V clamped by line clamping input are directly input to the sample and hold circuit. (2) Line Clamping Circuit This circuit is used for CCD (line clamping mode) and CIS3. The reference voltage (dark voltage) output in the shielding pixel part of the sensor is sampled by LCMP (line clamping pulses) and shifted up to the internal reference voltage of 2.2 V. This is not used for the CIS1 or CIS2 input sensor (set off constantly). : register 02 (LCMPS) REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 40 of 58 M66335FP (3) Sample and Hold Circuit and Bit Clamping Circuit In the CCD mode, bit clamping, as well as line clamping, can be performed. The blanking elements of each pixel of sensor output is sampled by BTCMP (bit clamping pulses). The differences of signals from the reference potential sampled by the bit clamping circuit are input to the gain control circuit of next step as signaling elements. To turn off bit clamping, set BLS invalid, so that the reference potential will be fixed at the internal reference potential of 2.2 V. : register 02 (BLS) (4) Gain Control Circuit The amplifying factor (gain) must be adjusted so that the amplitudes of sensor signals can come within the dynamic range of the A/D converter. The gain is set through the automatic gain control in the AGC mode (register 00) or directly through the register 18 (GAIN <7:0>). The gain changes within the following ranges according to the sensor used. Mode CCD CIS1 CIS2 CIS3 4 to 20 0.5 to 2.5 1 to 5 1 to 5 Amplifying Factor of Signals (Gain) In the AGC mode, the gain control counter is set at the greatest gain in the initial state and then counted down each time an overflow bit is output from the A/D converter. The count (gain) of the gain control counter is directly read/written through the register 18 (GAIN <7:0>). The counting operation of the counter can be controlled through the register 16 (AGCSTP). (5) Internal Reference Voltage Internal reference voltage source for the analog circuits: this generates the reference voltage (2.2 V) for the line clamping circuit, the sample and hold circuit, and the bit clamping circuit. A/D converter reference voltage generation circuit: this generates VWL (white level reference voltage of 3.8 V) and VBL (black level reference voltage of 1.8 V) for the A/D converter. (6) Black Level Clamping Circuit This circuit adjust the level of reference voltage to the A/D converter from analog circuits. The black clamping circuit is used in the CCD or CID3 mode. (See figure 18, 19 and 22) The GCAO pin and the BCMI pin are capacity-coupled. The output reference potential in the shielding pixel part of sensor signals are applied to the BCMV pin as the VBL (black level reference voltage of 1.8 V) for the A/D converter. BLCMP (black level clamping pulses) are generated concurrently with the shielding pixel part of each line. To turn off this circuit, set BLCMPS invalid and apply the black level reference voltage of the A/D converter to the BCMV pin. : register 02 (BLCMPS) In the CIS1 or CIS2 mode, the LEVAJ pin is used. (See figure 20 and 21) Voltage is applied to the LEVAJ pin so that the reference potential of output at the GCAO pin can be adjusted to the VBL (black level reference voltage of 1.8 V) of the A/D converter. Set voltage input to the LEVAJ pin as follows. VLEVAJ = VVBL - A x GV + 0.2 [V] VGCAO = VLEVAJ + GV x VIN [V] where, A: the lowest limit of dark voltage of the sensor [V] GV: gain (multiplying factor) of the gain control circuit VIN: signals input from the sensor [V] REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 41 of 58 AVcc DVcc BCMI BCMO Vcc M66335FP GCAO C1 C2 LEVAJ BCMV Vcc AVDD MCIS <3:1>, MCCD S/H BTCMP BLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO + - MCIS1 Sample and hold circuit Level shift circuit (2.2 V) LCMP MCIS <3:1>, MCCD S/H REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 42 of 58 AIN AIN MCIS2 - + + - V - + GCA + - - + - + - + BTCMP BLS BLCMP MCIS3 LCMP MCCD 8 - + - + Gain control circuit Bit clamping circuit 2.2 V Black level clamping circuit AGCSEL <7:0> RESET ADCK GAIN <7:0> Input clamping circuit - + + - Reference voltage generating circuit for the A/D converter + - Digital circuit Internal reference voltage source for the analog circuits Vri- AGND AVcc DVcc Vref- Vri+ Vref+ VREFH VREFL ADIN ADCK RESET 1.8 V 3.8 V AGND DGND OF B <7:1> OF DIN <6:0> A/D converter Figure 17 Circuit Configuration of the Analog Part of the M66335FP AGND DGND GND Vri- Vri+ VBL VWL ADIN GND VVBL = 1.8 [V] M66335FP Analog Circuit Timing Chart (for CCD Mode/Bit Clamping) Register Mode CCD (bit clamping) Address Bit Signal Setting 00H D6 SENS 1 D6 LCMPS 1 D5 BLS 1 D4 BLCMPS 1 02H D3 CCD 1 D2 CIS3 0 D1 CIS2 0 D0 CIS1 0 Non-signaling part SH CK1 CCD signal output LCMP BTCMP S/H GCAO signal output BLCMP Shielding pixel part Effective pixel part BCMO signal output A/D clock A/D output Non-signaling part 2 2 12 16 Shielding pixel part Effective pixel part Unit: 1/SYSCK SH CK1 CCD signal output N 16 3 4 9 LCMP 16 BTCMP S/H 16 13 2 3 4 9 1 GCAO signal output BLCMP N 8 8 BCMO signal output A/D clock A/D output N N REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 43 of 58 M66335FP Analog Circuit Timing Chart (for CCD Mode/Line Clamping) Register Mode CCD (line clamping) Address Bit Signal Setting 00H D6 SENS 1 D6 LCMPS 1 D5 BLS 0 D4 BLCMPS 1 02H D3 CCD 1 D2 CIS3 0 D1 CIS2 0 D0 CIS1 0 Non-signaling part SH CK1 CCD signal output LCMP BTCMP = "H" S/H GCAO signal output BLCMP Shielding pixel part Effective pixel part BCMO signal output A/D clock A/D output Non-signaling part SH CK1 CCD signal output 16 3 4 2 12 16 2 Shielding pixel part Effective pixel part Unit: 1/SYSCK N 9 LCMP BTCMP = "H" 16 S/H 3 4 9 GCAO signal output 8 8 N BLCMP BCMO signal output A/D clock A/D output N N REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 44 of 58 M66335FP Analog Circuit Timing Chart (for CIS1 Mode) Register Mode CIS1 Address Bit Signal Setting 00H D6 SENS 0 D6 LCMPS 0 D5 BLS 0 D4 BLCMPS 0 02H D3 CCD 0 D2 CIS3 0 D1 CIS2 0 D0 CIS1 1 SH CK1 CIS signal output LCMP = "H" BTCMP = "H" S/H GCAO signal output A/D clock A/D output Unit: 1/SYSCK SH CK1 10 4 2 16 16 CIS signal output LCMP = "H" BTCMP = "H" 16 N 7 S/H 4 1 GCAO signal output A/D clock N A/D output N REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 45 of 58 M66335FP Analog Circuit Timing Chart (for CIS2 Mode) Register Mode CIS2 Address Bit Signal Setting 00H D6 SENS 0 D6 LCMPS 0 D5 BLS 0 D4 BLCMPS 0 02H D3 CCD 0 D2 CIS3 0 D1 CIS2 1 D0 CIS1 0 SH CK1 CIS signal output LCMP = "H" BTCMP = "H" S/H GCAO signal output A/D clock A/D output SH CK1 Unit: 1/SYSCK 16 10 4 2 16 N CIS signal output LCMP = "H" BTCMP = "H" 16 7 S/H 4 1 GCAO signal output A/D clock N A/D output N REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 46 of 58 M66335FP Analog Circuit Timing Chart (for CIS3 Mode) Register Mode CIS3 Address Bit Signal Setting 00H D6 SENS 1 D6 LCMPS 1 D5 BLS 0 D4 BLCMPS 1 02H D3 CCD 0 D2 CIS3 1 D1 CIS2 0 D0 CIS1 0 Non-signaling part SH CK1 CIS signal output LCMP BTCMP = "H" S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Shielding pixel part Effective pixel part Non-signaling part SH 16 Shielding pixel part Effective pixel part Unit: 1/SYSCK CK1 CIS signal output LCMP 4 1 10 4 2 16 N BTCMP = "H" 16 7 S/H 4 1 GCAO signal output 8 8 N BLCMP BCMO signal output A/D clock N A/D output N REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 47 of 58 0.1 F LEVAJ = VBL BCMV = VBL M66335FP AVcc DVcc Vcc GCAO LEVAJ C1 C2 BCMV BCMI BCMO (bold line): signal line (dashed line): clock line 4 H Vcc AVDD MCIS <3:1>, MCCD S/H BTCMP BLS C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO Sensor output MCCD Bit clamping circuit AGCSEL <7:0> 2.2 V Reference voltage generating circuit for the A/D converter + - + - - + - + + - LCMP 8 Gain control circuit Black level clamping circuit Black Max 500 mVp-p White Input clamping circuit Signaling element - + Blanking element Internal reference voltage source for the analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+ AGND VREFH VREFL ADIN ADCK RESET 1.8 V 3.8 V AGND DGND A/D converter Figure 18 External Pin Connections of the Analog Part (for the CCD Mode/Bit Clamping) + - AGND DGND GND Vri- Vri+ VBL VWL ADIN - + REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 48 of 58 MCIS1 Sample and hold circuit Level shift circuit (2.2 V) LCMP MCIS <3:1>, MCCD S/H 0.1 F MCIS2 - + AIN - + AIN + - GCA V BTCMP BLS BLCMP RESET ADCK GAIN <7:0> MCIS3 - + - + Digital circuit OF B <7:1> OF DIN <6:0> GND 0.1 F LEVAJ = VBL GCAO LEVAJ BCMV BCMI BCMO C1 C2 BCMV = VBL M66335FP AVcc DVcc Vcc (bold line): signal line (dashed line): clock line 4 H Vcc L C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO AVDD MCIS <3:1>, MCCD S/H BTCMP BLS Sample and hold circuit + - - + LCMP MCCD Bit clamping circuit Input clamping circuit 2.2 V - + - + 8 Gain control circuit Black level clamping circuit Black Signaling element Blanking element + - Max 500 mVp-p White Reference voltage generating circuit for the A/D converter + - Internal reference voltage source for the analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+ AGND VREFH VREFL ADIN ADCK RESET 1.8 V 3.8 V AGND DGND A/D converter Figure 19 External Pin Connections of the Analog Part (for the CCD Mode/Line Clamping) + - AGND DGND GND Vri- Vri+ VBL VWL ADIN - + REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 49 of 58 MCIS1 Level shift circuit (2.2 V) LCMP MCIS <3:1>, MCCD S/H 0.1 F MCIS2 - + AIN - + AIN + - GCA V BTCMP BLS BLCMP RESET ADCK GAIN <7:0> MCIS3 - + - + AGCSEL <7:0> Digital circuit OF B <7:1> OF DIN <6:0> GND M66335FP Max 5 pF BCMV = VBL AVcc DVcc C1 C2 Vcc GCAO LEVAJ BCMV BCMI BCMO (bold line): signal line (dashed line): clock line 4 Vcc H H L L C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO AVDD MCIS <3:1>, MCCD S/H BTCMP BLS Sensor output MCCD Bit clamping circuit AGCSEL <7:0> 2.2 V - + + - - + LCMP 8 Max 3.5 V - + Gain control circuit Black level clamping circuit Black White Input clamping circuit Reference voltage generating circuit for the A/D converter + - + - 200 mV Internal reference voltage source for the analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+ AGND VREFH VREFL ADIN ADCK RESET 1.8 V 3.8 V AGND DGND Set R1 and R2 so that the following equation will hold. VLEVAJ = VVBL - A B + 0.2 [V] (1.8 V) Where, A/D converter A: minimum limit for dark voltage of the sensor Gr: gain of the gain control circuit Figure 20 External Pin Connections of the Analog Part (for the CIS1 Mode) + - MCIS1 Sample and hold circuit Level shift circuit (2.2 V) AGND DGND GND Vri- Vri+ VBL VWL R1 R2 VLEVAJ ADIN - + REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 50 of 58 LCMP MCIS <3:1>, MCCD S/H - + Sensor output MCIS2 - + AIN + - V BTCMP BLS BLCMP RESET ADCK GAIN <7:0> MCIS3 GCA - + - + Digital circuit OF B <7:1> OF DIN <6:0> GND Max 5 pF (In the case of the pixel clock of 1 MHz) M66335FP BCMV = VBL AVcc DVcc C1 C2 Vcc GCAO LEVAJ BCMV BCMI BCMO (bold line): signal line (dashed line): clock line 4 Vcc H H L L C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO AVDD MCIS <3:1>, MCCD S/H BTCMP BLS Sensor output - + - + + - LCMP 8 Bit clamping circuit AGCSEL <7:0> 2.2 V - + Gain control circuit Black level clamping circuit Black White Max 2 V MCCD Input clamping circuit 200 mV Reference voltage generating circuit for the A/D converter + - + - Internal reference voltage source for the analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+ AGND VREFH VREFL ADIN ADCK RESET 1.8 V 3.8 V AGND DGND Set R1 and R2 so that the following equation will hold. VLEVAJ = VVBL - A B + 0.2 [V] (1.8 V) Where, A/D converter A: minimum limit for dark voltage of the sensor Gr: gain of the gain control circuit Figure 21 External Pin Connections of the Analog Part (for the CIS2 Mode) + - MCIS1 Sample and hold circuit Level shift circuit (2.2 V) AGND DGND GND Vri- Vri+ VBL VWL R1 R2 ADIN VLEVAJ - + REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 51 of 58 LCMP MCIS <3:1>, MCCD S/H - + AIN MCIS2 MCIS3 GCA AIN - + + - V BTCMP BLS BLCMP RESET ADCK GAIN <7:0> - + - + Digital circuit OF B <7:1> OF DIN <6:0> GND 0.1 F LEVAJ = VBL BCMV = VBL M66335FP AVcc C1 C2 DVcc Vcc GCAO LEVAJ BCMV BCMI BCMO (bold line): signal line (dashed line): clock line 4 H Vcc L C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO AVDD MCIS <3:1>, MCCD 0.1 F MCIS2 - + AIN - + AIN + - V Sensor output MCCD Bit clamping circuit AGCSEL <7:0> 2.2 V - + + - - + LCMP 8 - + Gain control circuit White Input clamping circuit Max 2 Vp-p Black Shielding pixel part + - Signaling part Reference voltage generating circuit for the A/D converter + - Internal reference voltage source for the analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+ AGND VREFH VREFL ADIN ADCK RESET 1.8 V 3.8 V AGND DGND Figure 22 External Pin Connections of the Analog Part (for the CIS3 Mode) S/H BTCMP BLS Sample and hold circuit A/D converter AGND DGND GND Vri- Vri+ VBL VWL ADIN - + + - REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 52 of 58 MCIS1 Level shift circuit (2.2 V) LCMP MCIS <3:1>, MCCD S/H BTCMP BLS BLCMP Black level clamping circuit RESET ADCK GAIN <7:0> MCIS3 GCA - + - + Digital circuit OF B <7:1> OF DIN <6:0> GND M66335FP Flowchart Reading Operations (for the CCD Sensor) Start Power on Software reset S/H: SH pulse width Sensor control Cycle counter Start pulse Image processing parameters A Register 00 Register 01 Reading an original sheet starts. Image processing function Register 06 and 07 Register 00 Reading a single page Register 02 Specifying the scaling factor for vertical scanning Register 15 Register 03 and 04 SRDY setting Register 05 Initial setting Register 16 Register 08 to 0E Register 10 N INT generated? Register 17 Y N Page end? Y Reading the original sheet ends. Writing the dither pattern N Completed? Y Writing correction table N Next original sheet The light source is turned on. (white reference) Becomes stable. 1 line cycle x 20 (or 16 or more) wait Register 00 Register 0F Y 1 line cycle x 2 wait The light source is turned off. Transfer to be continued? Completed? Y AGC starts. Register 00 AGC: 16 times AGC ends. Register 00 Register 00 White correction : 8 times Register 00 Peak value detection White correction N Power off? N Next original sheet Y Next original sheet? Y Uniformity correction starts. N 1 line cycle x 10 (or 8 or more) wait Uniformity correction ends. Power off End Specifying the vertical scanning resolution Register 06 Setting for the original sheet Specifying the horizontal scanning resolution N Completed? Y Specifying the vertical scanning resolution Original sheet width and output width Register 15 Register 06 Registers 01 and 11 to 14 A REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 53 of 58 M66335FP Reading Operations (for the CIS Sensor) Start Power on Software reset S/H: SH pulse width Sensor control Cycle counter Start pulse Image processing parameters A Register 00 Register 01 Reading an original sheet starts. Image processing function Register 06 and 07 Register 00 Reading a single page Register 02 Specifying the scaling factor for vertical scanning Register 15 Registers 03 and 04 SRDY setting Initial setting Register 16 Register 05 Registers 08 to 0E Register 10 N INT generated? Register 17 Y N Page end? Y Writing the dither pattern N Completed? Y Writing correction table N Next original sheet The light source is turned on. (white reference) Becomes stable. 1 line cycle x 20 (or 16 or more) wait The light source is turned off. Reading the original sheet ends. Register 00 Y Register 0F 1 line cycle x 2 wait The light source is turned off. Transfer to be continued? N Completed? Y Peak value detection Power off? N Y Y AGC starts. Register 00 AGC: 16 times AGC ends. Register 00 Next original sheet Next original sheet? N Black correction Becomes stable. Uniformity correction mode (black) Uniformity correction starts. Registers 00 and 01 Power off End Register 00 Black correction: 8 times 1 line cycle x 10 (or 8 or more) wait The light source is turned on. (white reference) Becomes stable. Uniformity correction ends. Register 00 Uniformity correction mode (white) White correction Registers 00 and 01 Uniformity correction starts. Register 00 White correction: 8 times 1 line cycle x 10 (or 8 or more) wait Uniformity correction ends. Register 00 Specifying the horizontal scanning resolution Register 06 Setting for the original sheet Writing the resolution change table Register 15 N Completed? Y Register 06 Specifying the vertical scanning resolution Original sheet width and output width A Registers 01 and 11 to 14 REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 54 of 58 M66335FP MPU Interface Timing for Read Operation (M66335 MPU) 3V CS 1.3 V tSU (CS-RD) 1.3 V 0V th (RD-CS) 3V A0 to A4 1.3 V tSU (A-RD) tW (RD) 1.3 V 0V th (RD-A) 3V RD 1.3 V tPZL (RD-D) 1.3 V tPLZ (RD-D) 0V D0 to D7 tPZH (RD-D) 50% tPHZ (RD-D) 10% VOL D0 to D7 50% 90% VOH Timing for Write Operation (MPU M66335) 3V CS 1.3 V tSU (CS-WR) 1.3 V 0V th (WR-CS) 3V A0 to A4 1.3 V tSU (A-WR) tW (WR) 1.3 V 0V th (WR-A) 3V WR 1.3 V tSU (D-WR) 1.3 V 0V tSU (WR-D) 3V D0 to D7 1.3 V Effective data 1.3 V 0V REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 55 of 58 M66335FP DMA Timing Timing for Read Operation (M66335 System Bus) VOH DRQ 50% 120 / SYSCK tPHL (RD-DRQ) 50% VOL 3V DAK 1.3 V tSU (DAK-RD) tW (RD) 1.3 V 0V th (RD-DAK) 3V RD 1.3 V tPZL (RD-D) 1.3 V tPLZ (RD-D) 0V D0 to D7 tPZH (RD-D) 50% tPHZ (RD-D) 10% VOL D0 to D7 50% 90% VOH Timing of CODEC th (STIM-SRDY) SRDY 3V 1.3 V 0V VOH STIM 50% VOL VOH SCLK VOL VOH SVID VOL REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 56 of 58 M66335FP Cautions for Use (1) Access to Address 00h To gain access to address 00h, the value of built-in GCC (gain control counter) may be set to FFh. This requires to read GAIN value at address 18h before access to address 00h and write the GAIN value at address 18h after the access (see flowchart A). Start Read GAIN value at address 18h Access address 00h Write GAIN value at address 18h End Flowchart A Address 00h Access Flow (2) Reset The M66335FP adopts the two types of reset. These reset functions are provided in table A. Table A Reset Functions Function Reset Type Hardware reset (RESET) Software reset register 0 (RESET) Register Initialization Internal F/F Initialization GCC Initialization REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 57 of 58 M66335FP Package Dimensions JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g HD *1 D 41 64 65 40 ZE *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. HE E 80 25 Reference Symbol Dimension in Millimeters 1 ZD 24 Index mark F c D E A2 HD HE A A1 bp c L Detail F *3 REJ03F0276-0200 Rev.2.00 Jun 16, 2008 Page 58 of 58 A1 e y bp e y ZD ZE L Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 0.8 1.0 0.4 0.6 0.8 A A2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. 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